4.2.10 MOSCCTL Register (Offset = 0x7C) [reset = 0xC]
Main Oscillator Control (MOSCCTL)
This register provides control over the features of the main oscillator, including the ability to enable the MOSC clock verification circuit, what action to take when the MOSC fails, and whether or not a crystal is connected. When enabled, this circuit monitors the frequency of the MOSC to verify that the oscillator is operating within specified limits. If the clock goes invalid after being enabled, the microcontroller issues a power-on reset and reboots to the NMI handler or generates an interrupt.
NOTE
If the MOSC is chosen as the clock to the Ethernet PHY then software must enable the MOSC before enabling the Ethernet PHY by setting the P0 bit in the PCEPHY.
MOSCCTL is shown in Figure 4-16 and described in Table 4-20.
Return to Summary Table.
Figure 4-16 MOSCCTL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
OSCRNG |
PWRDN |
NOXTAL |
MOSCIM |
CVAL |
| R-0x0 |
R/W-0x0 |
R/W-0x1 |
R/W-0x1 |
R/W-0x0 |
R/W-0x0 |
|
Table 4-20 MOSCCTL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-5 |
RESERVED |
R |
0x0 |
|
| 4 |
OSCRNG |
R/W |
0x0 |
Oscillator Range
Specifies the frequency range of operation of the oscillator.
0x0 = Low-frequency range
0x1 = High-frequency range (equal to or greater than 10 MHz).
|
| 3 |
PWRDN |
R/W |
0x1 |
Power Down
Provides user control over powering down the main oscillator circuit. This bit should be cleared when using a crystal and set for single-ended mode.
0x0 = Power to MOSC circuit is enabled.
0x1 = MOSC circuit is powered down.
|
| 2 |
NOXTAL |
R/W |
0x1 |
No MOSC or Crystal Connected
Provides the user control over the power drawn from the main oscillator circuit. This bit should be set when either crystal or single-ended mode is being used. If the application needs MOSC, this bit should be cleared.
0x0 = This bit should be cleared when a crystal or oscillator is connected to the OSC0 and OSC1 inputs, regardless of whether or not the MOSC is used or powered down. For proper clock functionality when switching to crystal mode, software must clear this bit and set the PWRDN bit in a single write access.
0x1 = This bit should be set when a crystal or external oscillator is not connected to the OSC0 and OSC1 inputs to reduce power consumption.
|
| 1 |
MOSCIM |
R/W |
0x0 |
MOSC Failure Action
Regardless of the action taken, if the MOSC fails, the oscillator source is switched to the PIOSC automatically.
0x0 = If the MOSC fails, a MOSC failure reset is generated and reboots to the NMI handler.
0x1 = If the MOSC fails, an interrupt is generated as indicated by the MOSRIS bit in the RIS register.
|
| 0 |
CVAL |
R/W |
0x0 |
Clock Validation for MOSC
0x0 = The MOSC monitor circuit is disabled.
0x1 = The MOSC monitor circuit is enabled.
|