SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault.
Table 2-3 shows the encodings for the TEX, C, B, and S access permission bits. All encodings are shown for completeness, however the current implementation of the Cortex-M4 does not support the concept of cacheability or shareability. For information on programming the MPU for MSP432E4 implementations, see Section 2.2.4.2.1.
| TEX | S | C | B | Memory Type | Shareability | Other Attributes |
|---|---|---|---|---|---|---|
| 000b | x (1) | 0 | 0 | Strongly Ordered | Shareable | – |
| 000 | x(1) | 0 | 1 | Device | Shareable | – |
| 000 | 0 | 1 | 0 | Normal | Not shareable | Outer and inner write-through. No write allocate. |
| 000 | 1 | 1 | 0 | Normal | Shareable | |
| 000 | 0 | 1 | 1 | Normal | Not shareable | |
| 000 | 1 | 1 | 1 | Normal | Shareable | |
| 001 | 0 | 0 | 0 | Normal | Not shareable | Outer and inner noncacheable. |
| 001 | 1 | 0 | 0 | Normal | Shareable | |
| 001 | x(1) | 0 | 1 | Reserved encoding | – | – |
| 001 | x(1) | 1 | 0 | Reserved encoding | – | – |
| 001 | 0 | 1 | 1 | Normal | Not shareable | Outer and inner write-back. Write and read allocate. |
| 001 | 1 | 1 | 1 | Normal | Shareable | |
| 010 | x(1) | 0 | 0 | Device | Not shareable | Nonshared Device. |
| 010 | x(1) | 0 | 1 | Reserved encoding | – | – |
| 010 | x(1) | 1 | x(1) | Reserved encoding | – | – |
| 1BB | 0 | A | A | Normal | Not shareable | Cached memory (BB = outer policy, AA = inner policy).
See Table 2-4 for the encoding of the AA and BB bits. |
| 1BB | 1 | A | A | Normal | Shareable |
Table 2-4 shows the cache policy for memory attribute encodings with a TEX value in the range of 0x4 to 0x7.
| Encoding,
AA or BB |
Corresponding Cache Policy |
|---|---|
| 00 | Noncacheable |
| 01 | Write back, write and read allocate |
| 10 | Write through, no write allocate |
| 11 | Write back, no write allocate |
Table 2-5 shows the AP encodings in the MPUATTR register that define the access permissions for privileged and unprivileged software.
| AP Bit Field | Privileged Permissions | Unprivileged Permissions | Description |
|---|---|---|---|
| 000 | No access | No access | All accesses generate a permission fault. |
| 001 | RW | No access | Access from privileged software only. |
| 010 | RW | RO | Writes by unprivileged software generate a permission fault. |
| 011 | RW | RW | Full access. |
| 100 | Unpredictable | Unpredictable | Reserved. |
| 101 | RO | No access | Reads by privileged software only. |
| 110 | RO | RO | Read-only, by privileged or unprivileged software. |
| 111 | RO | RO | Read-only, by privileged or unprivileged software. |