SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
MPU Region Base Address (MPUBASE), offset 0xD9C
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4
NOTE
This register can only be accessed from privileged mode.
The MPUBASE register defines the base address of the MPU region selected by the MPU Region Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To change the current region number and update the MPUNUMBER register, write the MPUBASE register with the VALID bit set.
The ADDR field is bits 31: N of the MPUBASE register. Bits(N-1):5 are reserved. The region size, as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines the value of N where:
N = Log2(Region size in bytes)
If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64KB region must be aligned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000.
MPUBASEn is shown in Figure 2-31 and described in Table 2-46.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ADDR | |||||||
| R/W-0x0 | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ADDR | |||||||
| R/W-0x0 | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADDR | |||||||
| R/W-0x0 | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR | VALID | RESERVED | REGION | ||||
| R/W-0x0 | WO-0x0 | R-0x0 | R/W-0x0 | ||||