SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
To carry out this operation using DMA Mode 1, the DMA controller should be programmed as follows:
The USB Tx endpoint should be programmed as follows:
When the FIFO in the USB becomes available, the DMA controller requests bus mastership and transfer a packet to the FIFO. With the AUTOSET bit set, the USB automatically sets the TXRDY bit. This process continues until the entire data block has been transferred to the USB. The DMA controller then interrupts the processor. If the last packet to be loaded was less than the maximum packet size for the endpoint, the TXRDY bit is not set for this packet. The processor should therefore respond to the DMA interrupt by setting the TXRDY bit to allow the last short packet to be sent. If the last packet to be loaded was of the maximum packet size, then the action to take depends on whether the transfer is under the control of an application such as the mass storage software on a Windows system that keeps count of the individual packets sent. If the transfer is not under such control, the processor should still respond to the DMA interrupt by setting the TXRDY bit in the USB Transmit Control and Status Endpoint n Low (USBTXCSRLn) register. This has the effect of sending a null packet for the receiving software to interpret as indicating the end of the transfer.