| 31 |
USEALT |
R/W |
0x0 |
Two Wire Enable.
0x0 = Function in standard 1-Wire mode, using only the OWIRE signal for both input and output.
0x1 = Use the OWIRE signal for the input and the OWALT signal for the output.
|
| 30 |
ALTP |
R/W |
0x0 |
Alternate Polarity Enable.
0x0 = Output pin is driven low to drive 1-wire line low.
0x1 = Output pin is driven high to drive 1-Wire line low (that is, the output pin is connected to an NFET).
|
| 29-19 |
RESERVED |
R |
0x0 |
|
| 18-16 |
BSIZE |
R/W |
0x0 |
Last Byte Size. This field indicates the bit-size of the last byte. These bits are sent and received least significant bit first.
0x0 = 8 bits (1 byte)
0x1 = 1 bit
0x2 = 2 bits
0x3 = 3 bits
0x4 = 4 bits
0x5 = 5 bits
0x6 = 6 bits
0x7 = 7 bits
|
| 15-11 |
RESERVED |
R |
0x0 |
|
| 10 |
STUCK |
R |
0x0 |
STUCK Status.
0x0 = STUCK status is not detected.
0x1 = Indicates line is being held low (other than in normal operation). The STUCK bit in the ONEWIRERIS is asserted when a line-hold-low error is detected.
|
| 9 |
NOATR |
R |
0x0 |
Answer-to-Reset Status. This bit is disabled if the SKATR bit is set.
0x0 = Answer-to-reset behavior was as expected.
0x1 = No answer-to-reset was detected after last reset ( RST =1), which indicates no slave may be present on the bus.
|
| 8 |
BUSY |
R |
0x0 |
Busy Status.
0x0 = No activity on the bus.
0x1 = Activity is taking place on the bus as a result of a reset, read, write or read/write transaction.Because this bit is on the PIOSC clock domain, it does not set immediately when a read, write, read/write or reset transaction begins. The OPC and RST bits in the ONEWIRERIS register should be used to verify when these operations have completed.
|
| 7 |
SKATR |
R/W |
0x0 |
Skip Answer-to-Reset Enable.
0x0 = No effect.
0x1 = Transaction goes from reset to first byte transfer without an answer-to-reset (presence detect) after programmed rest period has passed.
|
| 6 |
LSAM |
R/W |
0x0 |
Late Sample Enable. This bit is used for long distance lines or when the slave cannot pull low quickly.
0x0 = Late sample disabled.
0x1 = 1-Wire module samples late in the read. The sample point moves to 50 µs for normal and 7 µs for overdrive (versus 16 µs and 2 µs in normal operation).
|
| 5 |
ODRV |
R/W |
0x0 |
Overdrive Enable.
0x0 = Overdrive mode disabled.
0x1 = Overdrive mode is enabled.
|
| 4-3 |
SZ |
R/W |
0x0 |
Data Operation Size. This field is used to program the size in bytes of data operations transferred to and from the ONEWIREDATn registers per request.
0x0 = 1 byte
0x1 = 2 bytes
0x2 = 3 bytes
0x3 = 4 bytes
|
| 2-1 |
OP |
R/W |
0x0 |
Operation Request. If written with a non-zero value, this field requests data operations on the 1-Wire bus for number of bytes configured by the SZ field. This field does not clear until the operation completes. The operation starts immediately. If using write or write/read, the ONEWIREDATW register must be written first. µDMA operations are handled by the ONEWIREDMA register.
0x0 = No operation
0x1 = Read
0x2 = Write
0x3 = Write/Read
|
| 0 |
RST |
R/W |
0x0 |
Reset Request. If RST = 1, a reset operation begins. This bit clears when the reset operation is complete and the NOATR bit can be read to verify that a slave responded. If this bit is set at the same time as the OP bit is set, the reset runs first and the operation starts when reset has completed. If this bit is written when an operation is already in progress, it cancels the operation and starts the reset.
0x0 = No effect.
0x1 = Reset operation request.
|