22.5.7 ONEWIREMIS Register (Offset = 0x108) [reset = 0x0]
1-Wire Masked Interrupt Status (ONEWIREMIS), offset 0x108
The 1-Wire Masked Interrupt Status (ONEWIREMIS) register indicates when an unmasked interrupt has occurred.
ONEWIREMIS is shown in Figure 22-13 and described in Table 22-11.
Return to Summary Table.
Figure 22-13 ONEWIREMIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DMA |
STUCK |
NOATR |
OPC |
RST |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 22-11 ONEWIREMIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-5 |
RESERVED |
R |
0x0 |
|
| 4 |
DMA |
R |
0x0 |
DMA Done Masked Interrupt Status.
0x0 = No interrupt
0x1 = A DMA transfer is complete and an unmasked interrupt is pending.
|
| 3 |
STUCK |
R |
0x0 |
Stuck Status Masked Interrupt Status. When unmasked, this interrupt indicates a line-hold-low error is detected.
0x0 = No interrupt
0x1 = An unmasked Stuck status (line-hold-error) interrupt is detected and pending.
|
| 2 |
NOATR |
R |
0x0 |
No Answer-to-Reset Masked Interrupt Status.
0x0 = No interrupt
0x1 = A No Answer-to-Reset unmasked interrupt is detected from the last reset and pending.
|
| 1 |
OPC |
R |
0x0 |
Operation Complete Masked Interrupt Status.
0x0 = No Interrupt
0x1 = An unmasked operation complete interrupt is pending.
|
| 0 |
RST |
R |
0x0 |
Reset Interrupt Mask.
0x0 = No Interrupt.
0x1 = The unmasked reset interrupt is pending.
|