22.5.6 ONEWIRERIS Register (Offset = 0x104) [reset = 0x0]
1-Wire Raw Interrupt Status (ONEWIRERIS), offset 0x104
The 1-Wire Raw Interrupt Status (ONEWIRERIS) register contains the raw interrupt status. If any of these bits read 1, the processor is interrupted if the corresponding masked interrupt status bit is set.
ONEWIRERIS is shown in Figure 22-12 and described in Table 22-10.
Return to Summary Table.
Figure 22-12 ONEWIRERIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DMA |
STUCK |
NOATR |
OPC |
RST |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 22-10 ONEWIRERIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-5 |
RESERVED |
R |
0x0 |
|
| 4 |
DMA |
R |
0x0 |
DMA Done Raw Interrupt Status.
0x0 = No interrupt
0x1 = DMA transfer complete and an interrupt is pending.
|
| 3 |
STUCK |
R |
0x0 |
Stuck Status Raw Interrupt Status. When unmasked, this interrupt indicates a line-hold-low error is detected.
0x0 = No interrupt
0x1 = Stuck status (line-hold-error) is detected and an interrupt is pending.
|
| 2 |
NOATR |
R |
0x0 |
No Answer-to-Reset Raw Interrupt Status.
0x0 = No interrupt
0x1 = A No Answer-to-Reset is detected from the last reset and an interrupt is pending.
|
| 1 |
OPC |
R |
0x0 |
Operation Complete Raw Interrupt Status. This bit indicates when a read, write or read/write operation has completed. If a read or read/write transfer has occurred then the read data is ready to be accessed when this bit is set.
0x0 = No interrupt.
0x1 = The last write, read, or write/read has completed and an interrupt is pending.
|
| 0 |
RST |
R |
0x0 |
Reset Raw Interrupt Status.
0x0 = No interrupt.
0x1 = The last reset completed and an interrupt is pending.
|