SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
An optional clock output, DIVSCLK, can be used as a clock source to an external device but bears no timing relationship to other signals. DIVSCLK is not synchronized to the system clock. By programming the SRC field in the Divisor and Source Clock Configuration (DIVSCLK) register, the following clock outputs can be selected for DIVSCLK:
The DIV field in the DIVSCLK register controls the divided output clock frequency. The DIVSCLK signal is selected as an alternate function of a GPIO signal and has the electrical characteristics of a GPIO (see the device-specific data sheet).