SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Micro Direct Memory Access Power Control (PCDMA)
NOTE
The µDMA module does not currently provide the ability to respond to the power-down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility.
The PCDMA register controls the power applied to the DMA module. The function of this bit depends on the current state of the device (run, sleep or deep-sleep mode) and value of the corresponding bits in the RCGCDMA, SCGCDMA, and DCGCDMA registers. If the Rn, Sn, or Dn bit of the respective RCGCDMA, SCGCDMA, and DCGCDMA registers is 1 and the device is in that mode, the module is powered and receives a clock regardless of what the corresponding Pn bit in the PCDMA register is.
However, if the Rn, Sn, or Dn bit of the respective RCGCDMA, SCGCDMA, and DCGCDMA registers is 0 and the device is in that mode, then the module behaves differently depending on the value of the corresponding Pn bit in the PCDMA register. In this case, when the Pn bit is clear, the module is not powered and does not receive a clock. If the Pn bit is set, the module is powered but does not receive a clock. Table 4-167 lists the differences.
| Rn, Sn, or Dn Value in Respective RCGCx, SCGCx, or DCGCx Register | Pn | Description |
|---|---|---|
| 0 | 0 |
Module is not powered and does not receive a clock. In this case, the state of the peripheral is not retained. This is the lowest power consumption state of any peripheral, because it consumes no dynamic nor leakage current. Hardware should perform a peripheral reset if the active mode changes and the RCGCx, SCGCx, or DCGCx register is 1 or the P0 bit is changed to 1. Software must reinitialize the peripheral when reenabled due to the loss of state. |
| 0 | 1 |
Module is powered but does not receive a clock. In this case, the peripheral is inactive. This is the second-lowest power consumption of any peripheral, because it consumes only leakage current. |
| 1 | X | Module is powered and receives a clock. |
PCDMA is shown in Figure 4-157 and described in Table 4-168.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0x0 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | P0 | ||||||||||||||
| R-0x0 | R/W-0x1 | ||||||||||||||