SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Interrupt 0-31 Set Pending (PEND0), offset 0x200
Interrupt 32-63 Set Pending (PEND1), offset 0x204
Interrupt 64-95 Set Pending (PEND2), offset 0x208
Interrupt 96-113 Set Pending (PEND3), offset 0x20C
NOTE
This register can only be accessed from privileged mode.
The PENDn registers force interrupts into the pending state and show which interrupts are pending. Bit 0 of PEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of PEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of PEND2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of PEND3 corresponds to Interrupt 96; bit 17 corresponds to interrupt 113.
See for interrupt assignments.
PENDn is shown in Figure 2-8 and described in Table 2-18.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT | |||||||||||||||||||||||||||||||
R/W-0x0 | |||||||||||||||||||||||||||||||