SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
When the device enters deep-sleep mode, software can further reduce power in peripheral modules that have their own associated memory array. Many of these peripherals can be programmed to enable a low-power retention mode or a power down of their associated peripheral SRAM array. If retention is supported and the PWRCTL bit field in the xMPC register is programmed to 0x1, the associated peripheral SRAM array enters retention mode and no accesses can be performed. When the PWRCTL bit is set to 0x0 in deep-sleep mode, the memory is powered off, the contents are lost, and the SRAM is not accessible. The Power Domain Status (xPDS) register of each peripheral can be read to determine the status of the memory array as well as the current power domain status of the peripheral. Table 4-7 lists the peripherals with SRAM arrays and their capabilities during low-power modes.
| Module | Memory Retention Capability? | Memory Array Power Down Capability? |
|---|---|---|
| USB | Yes | Yes |
| EMAC | No | Yes (only when power domain is off, PCEMAC register = 0x0) |
| LCD | No | No |
| CAN | No | Yes |