SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is tREADY (see the device-specific data sheet). During the relock time, the affected PLL is not usable as a clock reference. Software can poll the LOCK bit in the PLL Status (PLLSTAT) register to determine when the PLL has locked.
Do not modify the PLL VCO frequency while the PLL serves as a clock source to the system. All changes to the PLL must be performed using a different clock source until the PLL has locked frequency. Thus, changing the PLL VCO frequency must be done as a sequence from the PLL to PIOSC or MOSC and then PIOSC or MOSC to the new PLL.
Hardware is provided to keep the PLL from being used as a system clock until the tREADY condition is met after one of the previous changes. Software must ensure that the system is using a stable clock source (like the main oscillator) before the RSCLKCFG register is reprogrammed to enable the PLL. Software can use many methods to ensure that the system is clocked from the PLL, including periodically polling the PLLLRIS bit in the RIS register at offset 0x050, and enabling the PLL Lock interrupt in the IMC register at offset 0x054.