SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
PLL Frequency 1 (PLLFREQ1)
This register always contains the current Q and N values presented to the system PLL. If the PLL is reconfigured, it must go through a relock sequence, which requires approximately 128 PIOSC clocks. When controlling this register directly, software must change this value while the PLL is powered down. Writes to PLLFREQ0 are delayed from affecting the PLL until the RSCLKCFG register NEWFREQ bit is written as 1.
The MINT and MFRAC fields are present in the PLLFREQ0 register.
PLLFREQ1 is shown in Figure 4-26 and described in Table 4-32.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0x0 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | Q | RESERVED | N | ||||||||||||
| R-0x0 | R/W-0x0 | R-0x0 | R/W-0x0 | ||||||||||||