SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The PMT interrupt signal can be asserted when a valid remote wake-up frame or magic packet is received. The PMT interrupt signal restores the application clock and TX clock to the MAC. When the Ethernet MAC PMT Control and Status (EMACPMTCTLSTAT) register is read, the PMT interrupt is cleared in the EMACRIS register at least after four clock cycles of RX clock. When software resets the PWRDWN bit in the Ethernet MAC PMT Control and Status (EMACPMTCTLSTAT) register, the MAC comes out of the power-down mode, but this event does not generate at PMT interrupt.