SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
To save power, the application can disable the clock to the AES module when not in use. The AES is clock gated by setting the AESCFG bit in the Cryptographic Modules Clock Gating Request (CCMCGREQ) register, CRC and Cryptographic Modules (CCM) offset 0x204. The AES in addition to the DES, SHA/MD5 and CRC can also be clock gated as a group by setting the D0 bit in the CRC and Cryptographic Modules (DCGCCCM) register, System Control Module offset 0x874.