SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
To save power, the application can disable the clock to the SHA/MD5 module when not in use. The SHA/MD5 is clock gated by setting the SHACFG bit in the Cryptographic Modules Clock Gating Request (CCMCGREQ) register, CCM offset 0x204. The SHA in addition to the AES, DES, and Enhanced CRC can also be clock gated as a group by setting the D0 bit in the CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control (DCGCCCM) register, System Control Module offset 0x874.