SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Micro Direct Memory Access Peripheral Ready (PRDMA)
The PRDMA register indicates whether the µDMA module is ready to be accessed by software following a change in status of power, run mode clocking, or reset. A power change is initiated if the corresponding PCDMA bit is changed from 0 to 1. A run mode clocking change is initiated if the corresponding RCGCDMA bit is changed. A reset change is initiated if the corresponding SRDMA bit is changed from 0 to 1.
The PRDMA bit is cleared on any of the preceding events and is not set again until the module is completely powered, enabled, and internally reset.
PRDMA is shown in Figure 4-178 and described in Table 4-206.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0x0 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | R0 | ||||||||||||||
| R-0x0 | R-0x0 | ||||||||||||||