SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Interrupt 0-3 Priority (PRI0), offset 0x400
Interrupt 4-7 Priority (PRI1), offset 0x404
Interrupt 8-11 Priority (PRI2), offset 0x408
Interrupt 12-15 Priority (PRI3), offset 0x40C
Interrupt 16-19 Priority (PRI4), offset 0x410
Interrupt 20-23 Priority (PRI5), offset 0x414
Interrupt 24-27 Priority (PRI6), offset 0x418
Interrupt 28-31 Priority (PRI7), offset 0x41C
Interrupt 32-35 Priority (PRI8), offset 0x420
Interrupt 36-39 Priority (PRI9), offset 0x424
Interrupt 40-43 Priority (PRI10), offset 0x428
Interrupt 44-47 Priority (PRI11), offset 0x42C
Interrupt 48-51 Priority (PRI12), offset 0x430
Interrupt 52-55 Priority (PRI13), offset 0x434
Interrupt 56-59 Priority (PRI14), offset 0x438
Interrupt 60-63 Priority (PRI15), offset 0x43C
Interrupt 64-67 Priority (PRI16), offset 0x440
Interrupt 68-71 Priority (PRI17), offset 0x444
Interrupt 72-75 Priority (PRI18), offset 0x448
Interrupt 76-79 Priority (PRI19), offset 0x44C
Interrupt 80-83 Priority (PRI20), offset 0x450
Interrupt 84-87 Priority (PRI21), offset 0x454
Interrupt 88-91 Priority (PRI22), offset 0x458
Interrupt 92-95 Priority (PRI23), offset 0x45C
Interrupt 96-99 Priority (PRI24), offset 0x460
Interrupt 100-103 Priority (PRI25), offset 0x464
Interrupt 104-107 Priority (PRI26), offset 0x468
Interrupt 108-111 Priority (PRI27), offset 0x46C
Interrupt 112- 113 Priority (PRI28), offset 0x470
NOTE
This register can only be accessed from privileged mode.
The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows:
| PRIn Register Bit Field | Interrupt |
|---|---|
| Bits 31:29 | Interrupt [4n+3] |
| Bits 23:21 | Interrupt [4n+2] |
| Bits 15:13 | Interrupt [4n+1] |
| Bits 7:5 | Interrupt [4n] |
See for interrupt assignments.
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in the Application Interrupt and Reset Control (APINT) register (see Section 2.5.5) indicates the position of the binary point that splits the priority and subpriority fields.
These registers can only be accessed from privileged mode.
PRIn is shown in Figure 2-11 and described in Table 2-21.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| INTD | RESERVED | INTC | RESERVED | ||||||||||||
| R/W-0x0 | R-0x0 | R/W-0x0 | R-0x0 | ||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INTB | RESERVED | INTA | RESERVED | ||||||||||||
| R/W-0x0 | R-0x0 | R/W-0x0 | R-0x0 | ||||||||||||