24.5.9 QEIINTEN Register (Offset = 0x20) [reset = 0x0]
QEI Interrupt Enable (QEIINTEN)
This register contains enables for each of the QEI module interrupts. An interrupt is asserted to the interrupt controller if the corresponding bit in this register is set.
QEIINTEN is shown in Figure 24-12 and described in Table 24-11.
Return to Summary Table.
Figure 24-12 QEIINTEN Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
INTERROR |
INTDIR |
INTTIMER |
INTINDEX |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 24-11 QEIINTEN Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
INTERROR |
R/W |
0x0 |
Phase Error Interrupt Enable. The INTERROR bit is only applicable when the QEI is operating in quadrature phase mode (SIGMODE =0) and should be masked when SIGMODE =1.
0x0 = The INTERROR interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the INTERROR bit in the QEIRIS register is set.
|
| 2 |
INTDIR |
R/W |
0x0 |
Direction Change Interrupt Enable.
0x0 = The INTDIR interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the INTDIR bit in the QEIRIS register is set.
|
| 1 |
INTTIMER |
R/W |
0x0 |
Timer Expires Interrupt Enable.
0x0 = The INTTIMER interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the INTTIMER bit in the QEIRIS register is set.
|
| 0 |
INTINDEX |
R/W |
0x0 |
Index Pulse Detected Interrupt Enable.
0x0 = The INTINDEX interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the INTINDEX bit in the QEIRIS register is set.
|