24.5.11 QEIISC Register (Offset = 0x28) [reset = 0x0]
QEI Interrupt Status and Clear (QEIISC)
This register provides the current set of interrupt sources that are asserted to the controller. If a bit is set, the latched event has occurred and is enabled to generate an interrupt; if a bit is clear the event in question has not occurred or is not enabled to generate an interrupt. This register is RW1C; writing a 1 to a bit position clears the bit and the corresponding interrupt reason.
QEIISC is shown in Figure 24-14 and described in Table 24-13.
Return to Summary Table.
Figure 24-14 QEIISC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
INTERROR |
INTDIR |
INTTIMER |
INTINDEX |
| R-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
|
Table 24-13 QEIISC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
INTERROR |
R/W1C |
0x0 |
Phase Error Interrupt. This bit is cleared by writing a 1. Clearing this bit also clears the INTERROR bit in the QEIRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = The INTERROR bits in the QEIRIS register and the QEIINTEN registers are set, providing an interrupt to the interrupt controller.
|
| 2 |
INTDIR |
R/W1C |
0x0 |
Direction Change Interrupt. This bit is cleared by writing a 1. Clearing this bit also clears the INTDIR bit in the QEIRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = The INTDIR bits in the QEIRIS register and the QEIINTEN registers are set, providing an interrupt to the interrupt controller.
|
| 1 |
INTTIMER |
R/W1C |
0x0 |
Velocity Timer Expired Interrupt. This bit is cleared by writing a 1. Clearing this bit also clears the INTTIMER bit in the QEIRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = The INTTIMER bits in the QEIRIS register and the QEIINTEN registers are set, providing an interrupt to the interrupt controller.
|
| 0 |
INTINDEX |
R/W1C |
0x0 |
Index Pulse Interrupt. This bit is cleared by writing a 1. Clearing this bit also clears the INTINDEX bit in the QEIRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = The INTINDEX bits in the QEIRIS register and the QEIINTEN registers are set, providing an interrupt to the interrupt controller.
|