SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The Raster mode is enabled by setting the MODESEL bit in the LCD Control (LCDCTL) register. The following table shows the active external signals when this mode is active:
| Interface | Data Bus Width | RASTERCTRL
[9, 7, 1] |
Signal Name | Description |
|---|---|---|---|---|
| Passive (STN) Mono 4-bit | 4 | 001 | LCDDATA[3:0] | Data Bus |
| LCDCP | Pixel Clock | |||
| LCDLP | Horizontal clock (line clock) | |||
| LCDFP | Vertical clock (frame clock) | |||
| LCDAC | AC Bias | |||
| LCDMCLK | Not used | |||
| Passive (STN) Mono 8-bit | 8 | 101 | LCDDATA[7:0] | Data Bus |
| LCDCP | Pixel Clock | |||
| LCDLP | Horizontal clock (line clock) | |||
| LCDFP | Vertical clock (frame clock) | |||
| LCDAC | AC Bias | |||
| LCDMCLK | Not used | |||
| Passive (STN) Color | 8 | 100 | LCDDATA[7:0] | Data Bus |
| LCDCP | Pixel Clock | |||
| LCDLP | Horizontal clock (line clock) | |||
| LCDFP | Vertical clock (frame clock) | |||
| LCDAC | AC Bias | |||
| LCDMCLK | Not used | |||
| Active (TFT) Color | 16 | x10 | LCDDATA[15:0] | Data Bus |
| LCDCP | Pixel Clock | |||
| LCDLP | Horizontal clock (line clock) | |||
| LCDFP | Vertical clock (frame clock) | |||
| LCDAC | AC Bias | |||
| LCDMCLK | Not used |