SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The MAC transfers the received frames to the system memory only when the frame passes the address filter and the frame size is greater than or equal to configurable threshold bytes set for the RX FIFO, or when the complete frame is written to the RX FIFO in store-and-forward mode.
If the frame fails the address filtering, it is dropped in the MAC block unless the Receive All (RA) bit is set in the Ethernet MAC Frame Filter (EMACFRAMEFLTR), offset 0x004. If the RA bit is set, then the MAC passes all received frames. Frames that are shorter than 64 bytes, because of collision or premature termination, can be removed from the RX FIFO if the DFF bit is clear in the EMACDMAOPMODE register.
After 64 bytes have been received, the TX/RX Controller requests the DMA block to begin transferring the frame data to the receive buffer pointed by the current descriptor. The DMA sets the First Descriptor (RDES0[9]) bit to delimit the frame after the DMA Interface becomes ready to receive a data transfer (if DMA is not fetching transmit data from the system memory). The descriptors are released when the OWN (RDES0[31]) bit is reset to 0, either as the data buffer fills up or as the last segment of the frame is transferred to the receive buffer. If the frame is contained in a single descriptor, both Last Descriptor (RDES0[8]) and First Descriptor (RDES0[9]) are set.
The DMA fetches the next descriptor, sets the Last Descriptor (RDES0[8]) bit, and releases the RDES0 status bits in the previous frame descriptor. Then the DMA sets the RI bit of the EMACDMARIS register. The same process repeats unless the DMA encounters a descriptor flagged as being owned by the host. If this occurs, the receive process sets the RU bit of the EMACDMARIS and enters the SUSPEND state. The position in the receive list is retained.