SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
If a new receive frame arrives while the receive process is in SUSPEND state, the DMA refetches the current descriptor in the system memory. If the descriptor is now owned by the DMA, the receive process re-enters the RUN state and starts frame reception. If the descriptor is still owned by the CPU, by default, the DMA discards the current frame at the top of the RX FIFO and increments the missed frame counter. If more than one frame is stored in the RX FIFO, the process repeats. The discarding or flushing of the frame at the top of the RX FIFO can be prevented by disabling flushing through the DFF bit of the EMACDMAOPMODE register. In such conditions, the receive process sets the Receive Buffer Unavailable (RU) status and returns to the SUSPEND state.