SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Because the WDT1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. Software must guarantee that this delay is inserted between back-to-back writes to WDT1 registers or between a write followed by a read to the registers. The timing for back-to-back reads from the WDT1 module has no restrictions. The WRC bit in the Watchdog Control (WDTCTL) register for WDT1 indicates that the required timing gap has elapsed. This bit is cleared on a write operation and set when the write completes, indicating to software that another write or read may be started safely. Software should poll WDTCTL for WRC = 1 prior to accessing another register. Note that WDT0 does not have this restriction as it runs off the system clock.