SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The I2C master module can execute a repeated START (transmit or receive) after an initial transfer has occurred.
NOTE
When reading the I2CMCS register to check the BUSY bit, also read the ADRACK and DATACK bits, because these are cleared on register read, and status may be lost if they are not checked on every read of the register.
Alternatively, the NACKRIS bit of the I2CMRIS register can be used to monitor NACK status.
For more information on repeated START, see Figure 19-12 and Figure 19-13.