4.2.30 RESBEHAVCTL Register (Offset = 0x1D8) [reset = 0x00FFFFFF]
Reset Behavior Control Register (RESBEHAVCTL)
The Reset Behavior Control Register contains system management controls.
The RESBEHAVCTL register effect occurs immediately when the register is changed. The next power-on reset sequence returns the reset value.
If any of the following bit fields are set to 0x3 when a reset occurs, a simulated POR is generated and the appropriate reset cause is set in the Reset Cause (RESC) register. During a simulated POR, registers are reloaded and the bootloader is executed. If a full POR is initiated, the POR bit in the RESC register is set and all other bits are cleared.
RESBEHAVCTL is shown in Figure 4-36 and described in Table 4-43.
Return to Summary Table.
Figure 4-36 RESBEHAVCTL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0xFFFF |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
WDOG1 |
WDOG0 |
BOR |
EXTRES |
| R-0xFFFF |
R/W-0x3 |
R/W-0x3 |
R/W-0x3 |
R/W-0x3 |
|
Table 4-43 RESBEHAVCTL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-8 |
RESERVED |
R |
0xFFFF |
|
| 7-6 |
WDOG1 |
R/W |
0x3 |
Watchdog 1 Reset Operation
0x0 = Reserved. Default operation is performed.
0x2 = Watchdog 1 issues a system reset.
0x3 = Watchdog 1 issues a simulated POR sequence (default).
|
| 5-4 |
WDOG0 |
R/W |
0x3 |
Watchdog 0 Reset Operation
0x0 = Reserved. Default operation is performed.
0x2 = Watchdog 0 issues a system reset.
0x3 = Watchdog 0 issues a simulated POR sequence (default).
|
| 3-2 |
BOR |
R/W |
0x3 |
BOR Reset operation. This field defines operation of BOR when the user has defined the BOR operation to be a reset. If the BOR operation is defined as an interrupt, this setting has no effect.
0x0 = Reserved. Default operation is performed.
0x2 = Brownout reset issues system reset.
0x3 = Brownout reset issues a simulated POR sequence (default).
|
| 1-0 |
EXTRES |
R/W |
0x3 |
External RST Pin Operation
0x0 = Reserved. Default operation is performed.
0x2 = External RST assertion issues a system reset.
0x3 = External RST assertion issues a simulated POR sequence (default).
|