SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Reset Cause (RESC)
This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences. If a full POK-POR is initiated, the POR bit in the RESC register is set and all other bits are cleared. If the WDOGn, BOR or EXTRES configuration fields are set to 0x3 in the RESBEHAVCTL register and a simulated POR is initiated, the cause of the reset is reflected in the RESC register.
NOTE
After the RESC register is read, the Hibernate Raw Interrupt Status (HIBRIS) register in the Hibernation module must be evaluated to determine the full cause of the reset. Although an external reset assertion or POR resulting from a wake event is registered in the RESC register, the specific external wake source, including a low battery detect, is only registered in the HIBRIS register.
RESC is shown in Figure 4-13 and described in Table 4-17.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | MOSCFAIL | ||||||
R-0x0 | R/W-X | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | HSSR | RESERVED | |||||
R-0x0 | R/W-X | R-0x0 | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WDT1 | SW | WDT0 | BOR | POR | EXT | |
R-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x1 | R/W-0x0 | |