4.2.4 RIS Register (Offset = 0x50) [reset = 0x0]
Raw Interrupt Status (RIS)
This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing 1 to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt status bit.
RIS is shown in Figure 4-10 and described in Table 4-14.
Return to Summary Table.
Figure 4-10 RIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
MOSCPUPRIS |
| R-0x0 |
R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
PLLLRIS |
RESERVED |
MOFRIS |
RESERVED |
BORRIS |
RESERVED |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 4-14 RIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-9 |
RESERVED |
R |
0x0 |
|
| 8 |
MOSCPUPRIS |
R |
0x0 |
MOSC Power Up Raw Interrupt Status.
This bit is cleared by writing 1 to the MOSCPUPMIS bit in the MISC register.
0x0 = Sufficient time has not passed for the MOSC to reach the expected frequency.
0x1 = Sufficient time has passed for the MOSC to reach the expected frequency. The value for this power-up time is indicated by TMOSC_START.
|
| 7 |
RESERVED |
R |
0x0 |
|
| 6 |
PLLLRIS |
R |
0x0 |
PLL Lock Raw Interrupt Status.
This bit is cleared by writing 1 to the PLLLMIS bit in the MISC register.
0x0 = The PLL timer has not reached TREADY.
0x1 = The PLL timer has reached TREADYindicating that sufficient time has passed for the PLL to lock.
|
| 5-4 |
RESERVED |
R |
0x0 |
|
| 3 |
MOFRIS |
R |
0x0 |
Main Oscillator Failure Raw Interrupt Status.
This bit is cleared by writing 1 to the MOFMIS bit in the MISC register.
0x0 = The main oscillator has not failed.
0x1 = The MOSCIM bit in the MOSCCTL register is set and the main oscillator has failed.
|
| 2 |
RESERVED |
R |
0x0 |
|
| 1 |
BORRIS |
R |
0x0 |
Brownout Reset Raw Interrupt Status.
The appropriate BOR bit in the PTBOCTL register must be set to an interrupt (0x1) encoding to generate an interrupt. . This bit is cleared by writing 1 to the BORMIS bit in the MISC register.
0x0 = A brownout condition is not currently active.
0x1 = A brownout condition is currently active.
|
| 0 |
RESERVED |
R |
0x0 |
|