4.1.5.2.1.3.3 RMII Interface Clocking
Three clock sources interface to the Ethernet MAC in an RMII configuration (see Section 15.3.1.3 for more information):
- Gated system clock (SysClk): The SysClk signal acts as the clock source to the CSRs of the Ethernet MAC. The SysClk frequency for run, sleep, and deep-sleep modes is programmed in the System Control module.
- MOSC: A gated version of the MOSC clock is provided as the PTP reference clock (PTPREF_CLK). The MOSC clock source can be a single-ended source on the OSC0 pin or a crystal on the OSC0 and OSC1 pins. When advanced timestamping is used and the PTP module has been enabled by setting the PTPCEN bit in the EMACCC register, the MOSC drives PTPREF_CLK. PTPREF_CLK has a minimum frequency requirement of 5 MHz and a maximum frequency of 25 MHz. See Section 15.3.6 for more information.
- EN0REF_CLK: When using RMII, a 50-MHz external reference clock must drive the reference clock input signal (EN0REF_CLK) and the external PHY. Depending on the configuration of the FES bit in the Ethernet MAC Configuration (EMACCFG) register, the EN0REF_CLK is divided by 20 for 10-Mbps operation or by 2 for 100-Mbps operation and is used as the clock for receive and transmit data.