| 31 |
MEMTIMU |
R0/W |
0x0 |
Memory Timing Register Update.
Setting this bit causes the MEMTIM0 register value to be applied, and the memory timing to be updated. Execution and access is suspended during the change. This bit is automatically cleared by hardware. |
| 30 |
NEWFREQ |
R0/W |
0x0 |
New PLLFREQ Accept.
This bit controls the activation of the values in the PLLFREQ0 and PLLFREQ1 registers as applied to the PLL. Until NEWFREQ is written to a 1, writes to the PLLFREQ0 and PLLFREQ1 are deferred. When written with a 1, the values stored in PLLFREQ0 and PLLFREQ1 are applied to the PLL. This bit is automatically cleared by hardware. Software will not check the value after being set. |
| 29 |
ACG |
R/W |
0x0 |
Auto Clock Gating.
This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the microcontroller enters a sleep or deep-sleep mode (respectively). The RCGCn registers are always used to control the clocks in run mode.
0x0 = The Run-Mode Clock Gating Control (RCGCn) registers are used when the microcontroller enters a sleep mode.
0x1 = If the microcontroller is in sleep mode, the SCGCn registers are used to control the clocks distributed to the peripherals. If the microcontroller is in deep-sleep mode, the DCGCn registers are used to control the clocks distributed to the peripherals. The SCGCn and DCGCn registers allow unused peripherals to consume less power when the microcontroller is in a sleep mode.
|
| 28 |
USEPLL |
R/W |
0x0 |
Use PLL.
This bit controls whether the clock source is specified by the OSCSRC field or the output of the PLL is provided to the system clock divider and serves as the system clock source.
0x0 = Clock source is specified by the OSCSRC field.
0x1 = Clock source is specified by the PLL.
|
| 27-24 |
PLLSRC |
R/W |
0x0 |
PLL Source.
This field specifies the PLL input clock source.
0x0 = Reserved
0x3 = MOSC is the PLL input clock source
|
| 23-20 |
OSCSRC |
R/W |
0x0 |
Oscillator Source.
This field specifies the oscillator source that becomes the oscillator clock (OSCCLK) source, which is used when the PLL is bypassed during run or sleep modes.
0x0 = Reserved
0x1 = Reserved
0x2 = LFIOSC is the oscillator source.
0x3 = MOSC is the oscillator source.
0x4 = Hibernation module RTC oscillator (RTCOSC)
|
| 19-10 |
OSYSDIV |
R/W |
0x0 |
Oscillator System Clock Divisor.
This field specifies the system clock divisor value for the oscillator path. This field is used when the USEPLL bit is 0.
fsyclk = foscclk / (OSYSDIV + 1)
The divisor value is the OSYSDIV field value + 1 |
| 9-0 |
PSYSDIV |
R/W |
0x0 |
PLL System Clock Divisor.
This field specifies the system clock divisor value for the PLL. This field is used when the USEPLL bit is 1.
fsyclk = fVCO / (PSYSDIV + 1) |