SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The Hibernation module includes a 32-bit match register, HIBRTCM0, which is compared to the value of the RTC 32-bit counter, HIBRTCC. The match functionality also extends to the subseconds counter. The 15-bit field (RTCSSM) in the HIBRTCSS register is compared to the value of the 15-bit subseconds counter. When a match occurs, the RTCALT0 bit is set in the HIBRIS register. For applications using Hibernate mode, the processor can be programmed to wake from Hibernate mode by setting the RTCWEN bit in the HIBCTL register. The processor can also be programmed to generate an interrupt to the interrupt controller by setting the RTCALT0 bit in the HIBIM register.
The match interrupt generation takes priority over an interrupt clear. Therefore, writes to the RTCALT0 bit in the Hibernation Interrupt Clear (HIBIC) register do not clear the RTCALT0 bit if the HIBRTCC value and the HIBRTCM0 value are equal. There are several methodologies to avoid this occurrence, such as writing a new value to the HIBRTCLD register prior to writing the HIBIC to clear the RTCALT0. Another example, would be to disable the RTC and re-enable the RTC by clearing and setting the RTCEN bit in the HIBCTL register.
NOTE
A Hibernate request made while a match event is valid causes the module to immediately wake up. This occurs when the RTCWEN bit is set and the RTCALT0 bit in the HIBRIS register is set at the same time the HIBREQ bit in the HIBCTL register is written to a 1. This can be avoided by clearing the RTCAL0 bit in the HIBRIS register by writing a 1 to the corresponding bit in the HIBIC register before setting the HIBREQ bit. Another example would be to disable the RTC and re-enable the RTC by clearing and setting the RTCEN bit in the HIBCTL register.