SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
In Run mode, the microcontroller actively executes code. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the peripheral-specific RCGC registers. In run mode (and in sleep mode), the Run and Sleep Clock Configuration (RSCLKCFG) register specifies the source of SysClk. The source is either from the VCO output of the PLL divided down (using the Q divider) or from the output of an oscillator divided down by a dedicated divisor (divisor value specified by the OSYSDIV field). The source is selected using the USEPLL bit in the RSCLKCFG register. The PLL has two sources of reference clock as an input: the main oscillator (MOSC) or the precision internal oscillator (PIOSC). The PLL input select is specified by PLLSRC. If the PLL VCO output is not selected as the source of SysClk then the following reference clocks can be programmed as an input:
These alternate sources are selected through the OSCSRC field in the RSCLKCFG register.