SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The ADC module provides the capability of programming the sample and hold window of each step in a sequence through the ADC Sample Sequence n Sample and Hold Time (ADCSSTSHn) register. Each TSHn field can be written with a different sample and hold width, which is represented in ADC clocks. Table 10-2 lists the allowed encodings:
| TSHn Encoding | NSH |
|---|---|
| 0x0 | 4 |
| 0x1 | Reserved |
| 0x2 | 8 |
| 0x3 | Reserved |
| 0x4 | 16 |
| 0x5 | Reserved |
| 0x6 | 32 |
| 0x7 | Reserved |
| 0x8 | 64 |
| 0x9 | Reserved |
| 0xA | 128 |
| 0xB | Reserved |
| 0xC | 256 |
| 0xD-0xF | Reserved |
The ADC conversion frequency is a function of the Sample and Hold number, given by the following equation:
fCONV = 1 / ((NSH + 12) × TADC)
where:
Now, the maximum allowable external source resistance (RS) also changes with the value of NSH, as the total settling time of the input circuitry must be fast enough to settle to within the ADC resolution in a single sampling interval. The input circuitry includes the external source resistance as well as the input resistance and capacitance of the ADC (RADC and CADC).
The values for RS and fCONV for varying NSH values, with fADC = 16 MHz and fADC = 32 MHz are given in tables 18-4-a and 18-4-b. The system designer must take into consideration both of these factors for optimal ADC operation.
| NSH (Cycles) | 4 | 8 | 16 | 32 | 64 | 128 | 256 |
|---|---|---|---|---|---|---|---|
| fCONV (ksps) | 1000 | 800 | 571 | 364 | 211 | 114 | 60 |
| RS max (Ω) | 500 | 3500 | 9500 | 21500 | 45500 | 93500 | 189500 |
| NSH (Cycles) | 4 | 8 | 16 | 32 | 64 | 128 | 256 |
|---|---|---|---|---|---|---|---|
| fCONV (ksps) | 2000 | 1600 | 1143 | 727 | 421 | 229 | 119 |
| RS max (Ω) | 250 | 500 | 3500 | 9500 | 21500 | 45500 | 93500 |