SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The Ethernet MAC module has the capability of programming the integrated PHY registers and extended registers through an internal Serial Management Interface (SMI). The SMI is compatible with IEEE 802.3-2002 clause 22.
The SMI includes an MDC management clock input and management MDIO data pin to the Ethernet PHY. The internal MDC clock is sourced by the system clock and then divided down to the required 2.5-MHz maximum clock frequency by setting the CR bit in the Ethernet MAC MII Address (EMACMIIADDR) register. The MDC is not expected to be continuous, and can be turned off by the external management entity when the bus is idle. The MDIO is sourced by the integrated MAC and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC clock. The PHY's physical address is 0x00.