25.3.1 SHA_DMAIM Register (Offset = 0x10) [reset = 0x0]
SHA DMA Interrupt Mask (SHA_DMAIM)
The SHA DMA Interrupt Mask (SHA_DMA_IM) register controls interrupt behavior and are used to program which interrupts are suppressed.
SHA_DMAIM is shown in Figure 25-14 and described in Table 25-27.
Return to Summary Table.
Figure 25-14 SHA_DMAIM Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
COUT |
DIN |
CIN |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 25-27 SHA_DMAIM Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-3 |
RESERVED |
R |
0x0 |
|
| 2 |
COUT |
R/W |
0x0 |
Context Out DMA Done Interrupt Mask.
If this bit is unmasked, an interrupt is generated when the µDMA completes the output context read from the internal register.
0x0 = The COUT interrupt is suppressed and not sent to the interrupt controller.
0x1 = The COUT interrupt is sent to the interrupt controller.
|
| 1 |
DIN |
R/W |
0x0 |
Data In DMA Done Interrupt Mask.
If this bit is unmasked, an interrupt is generated when the µDMA writes the last word of input data to the internal FIFO of the engine.
0x0 = The DIN interrupt is suppressed and not sent to the interrupt controller.
0x1 = The DIN interrupt is sent to the interrupt controller.
|
| 0 |
CIN |
R/W |
0x0 |
Context In DMA Done Interrupt Mask.
If this bit is unmasked, an interrupt is generated when the µDMA completes a context write to the internal register.
0x0 = The CIN interrupt is suppressed and not sent to the interrupt controller.
0x1 = The CIN interrupt is sent to the interrupt controller.
|