25.2.9 SHA_IRQSTATUS Register (Offset = 0x118) [reset = 0x8]
SHA Interrupt Status (SHA_IRQSTATUS)
SHA_IRQSTATUS is shown in Figure 25-12 and described in Table 25-23.
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Figure 25-12 SHA_IRQSTATUS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
CONTEXT_READY |
RESERVED |
INPUT_READY |
OUTPUT_READY |
| R-0x0 |
R-0x1 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 25-23 SHA_IRQSTATUS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
CONTEXT_READY |
R |
0x1 |
Context Ready Status
0x0 = The context registers are not available for a new context.
0x1 = The context input registers are available for a new context for the next packet to be processed.
|
| 2 |
RESERVED |
R |
0x0 |
|
| 1 |
INPUT_READY |
R |
0x0 |
Input Ready Status
0x0 = The Data FIFO is not ready to receive the next 64-byte data block.
0x1 = The Data FIFO (SHA_DATA_n_IN registers) is ready to receive the next 64-byte data block.
|
| 0 |
OUTPUT_READY |
R |
0x0 |
Output Ready Status
0x0 = No saved context available.
0x1 = A saved context is available from the context output registers.
|