SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The SHA Module registers are at an offset relative to the SHA/MD5 Module base address, and a small set of SHA/MD5 µDMA interrupt registers are at an offset relative to a CRC and Cryptographic module base address.
The SHA/MD5 module register offsets are relative to the base address 0x44034000.
The SHA/MD5 registers are limited to 32-bit data accesses; 8- and 16-bit accesses are not allowed and can corrupt register contents.The first 16 registers of HIB1 are the outer and inner digest registers (see Table 25-12).
| Register Name | Address Offset | MD5
(read/write) |
SHA-1
(read/write) |
SHA-2
(read/write) |
HMAC key proc
(write) |
|
|---|---|---|---|---|---|---|
| SHA_ODIGEST_A | 0x0000 | Outer digest [127:96] | Outer digest [159:128] | Outer digest [255:224] | HMAC key [31,0] | |
| SHA_ODIGEST_B | 0x0004 | Outer digest [95:64] | Outer digest [127:96] | Outer digest [223:192] | HMAC key [63,32] | |
| SHA_ODIGEST_C | 0x0008 | Outer digest [63:32] | Outer digest [95:64] | Outer digest [191:160] | HMAC key [95,64] | |
| SHA_ODIGEST_D | 0x000C | Outer digest [31:0] | Outer digest [63:32] | Outer digest [159:128] | HMAC key [127,96] | |
| SHA_ODIGEST_E | 0x0010 | Outer digest [31:0] | Outer digest [127:96] | HMAC key [159,128] | ||
| SHA_ODIGEST_F | 0x0014 | Outer digest [95:64] | HMAC key [191,160] | |||
| SHA_ODIGEST_G | 0x0018 | Outer digest [63:32] | HMAC key [223,192] | |||
| SHA_ODIGEST_H | 0x001C | Outer digest [31:0] | HMAC key [255,224] | |||
| SHA_IDIGEST_A | 0x0020 | Inner digest [127:96] | Inner digest [159:128] | Inner digest [223:192] | Inner digest [255:224] | HMAC key [287,256] |
| SHA_IDIGEST_B | 0x0024 | Inner digest [95:64] | Inner digest [127:96] | Inner digest [191:160] | Inner digest [223:192] | HMAC key [319,288] |
| SHA_IDIGEST_C | 0x0028 | Inner digest [63:32] | Inner digest [95:64] | Inner digest [159:128] | Inner digest [191:160] | HMAC key [351,320] |
| SHA_IDIGEST_D | 0x002C | Inner digest [31:0] | Inner digest [63:32] | Inner digest [127:96] | Inner digest [159:128] | HMAC key [383,352] |
| SHA_IDIGEST_E | 0x0030 | Inner digest[31:0] | Inner digest [95:64] | Inner digest [127:96] | HMAC key [415,384] | |
| SHA_IDIGEST_F | 0x0034 | Inner digest [63:32] | Inner digest [95:64] | HMAC key [447,416] | ||
| SHA_IDIGEST_G | 0x0038 | Inner digest [31:0] | Inner digest [63:32] | HMAC key [479,448] | ||
| SHA_IDIGEST_H | 0x003C | Inner digest[31:0] | HMAC key [511,480] |
Table 25-13 lists the memory-mapped registers for the SHA/MD5. All register offset addresses not listed in Table 25-13 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x000 | SHA_ODIGEST_A | SHA Outer Digest A | Section 25.2.1 |
| 0x004 | SHA_ODIGEST_B | SHA Outer Digest B | Section 25.2.1 |
| 0x008 | SHA_ODIGEST_C | SHA Outer Digest C | Section 25.2.1 |
| 0x00C | SHA_ODIGEST_D | SHA Outer Digest D | Section 25.2.1 |
| 0x010 | SHA_ODIGEST_E | SHA Outer Digest E | Section 25.2.1 |
| 0x014 | SHA_ODIGEST_F | SHA Outer Digest F | Section 25.2.1 |
| 0x018 | SHA_ODIGEST_G | SHA Outer Digest G | Section 25.2.1 |
| 0x01C | SHA_ODIGEST_H | SHA Outer Digest H | Section 25.2.1 |
| 0x020 | SHA_IDIGEST_A | SHA Inner Digest A | Section 25.2.1 |
| 0x024 | SHA_IDIGEST_B | SHA Inner Digest B | Section 25.2.1 |
| 0x028 | SHA_IDIGEST_C | SHA Inner Digest C | Section 25.2.1 |
| 0x02C | SHA_IDIGEST_D | SHA Inner Digest D | Section 25.2.1 |
| 0x030 | SHA_IDIGEST_E | SHA Inner Digest E | Section 25.2.1 |
| 0x034 | SHA_IDIGEST_F | SHA Inner Digest F | Section 25.2.1 |
| 0x038 | SHA_IDIGEST_G | SHA Inner Digest G | Section 25.2.1 |
| 0x03C | SHA_IDIGEST_H | SHA Inner Digest H | Section 25.2.1 |
| 0x040 | SHA_DIGEST_COUNT | SHA Digest Count | Section 25.2.2 |
| 0x044 | SHA_MODE | SHA Mode | Section 25.2.3 |
| 0x048 | SHA_LENGTH | SHA Length | Section 25.2.4 |
| 0x080 | SHA_DATA_0_IN | SHA Data 0 Input | Section 25.2.5 |
| 0x084 | SHA_DATA_1_IN | SHA Data 1 Input | Section 25.2.5 |
| 0x088 | SHA_DATA_2_IN | SHA Data 2 Input | Section 25.2.5 |
| 0x08C | SHA_DATA_3_IN | SHA Data 3 Input | Section 25.2.5 |
| 0x090 | SHA_DATA_4_IN | SHA Data 4 Input | Section 25.2.5 |
| 0x094 | SHA_DATA_5_IN | SHA Data 5 Input | Section 25.2.5 |
| 0x098 | SHA_DATA_6_IN | SHA Data 6 Input | Section 25.2.5 |
| 0x09C | SHA_DATA_7_IN | SHA Data 7 Input | Section 25.2.5 |
| 0x0A0 | SHA_DATA_8_IN | SHA Data 8 Input | Section 25.2.5 |
| 0x0A4 | SHA_DATA_9_IN | SHA Data 9 Input | Section 25.2.5 |
| 0x0A8 | SHA_DATA_10_IN | SHA Data 10 Input | Section 25.2.5 |
| 0x0AC | SHA_DATA_11_IN | SHA Data 11 Input | Section 25.2.5 |
| 0x0B0 | SHA_DATA_12_IN | SHA Data 12 Input | Section 25.2.5 |
| 0x0B4 | SHA_DATA_13_IN | SHA Data 13 Input | Section 25.2.5 |
| 0x0B8 | SHA_DATA_14_IN | SHA Data 14 Input | Section 25.2.5 |
| 0x0BC | SHA_DATA_15_IN | SHA Data 15 Input | Section 25.2.5 |
| 0x100 | SHA_REVISION | SHA Revision | Section 25.2.6 |
| 0x110 | SHA_SYSCONFIG | SHA System Configuration | Section 25.2.7 |
| 0x114 | SHA_SYSSTATUS | SHA System Status | Section 25.2.8 |
| 0x118 | SHA_IRQSTATUS | SHA Interrupt Status | Section 25.2.9 |
| 0x11C | SHA_IRQENABLE | SHA Interrupt Enable | Section 25.2.10 |
Complex bit access types are encoded to fit into small table cells. Table 25-14 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |