SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
In sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered by the Cortex-M4F core executing a WFI (Wait for Interrupt) instruction. Any properly configured interrupt event in the system returns the processor to run mode. See Section 1.8 for more details.
Peripherals are clocked if enabled in the peripheral-specific SCGC registers when automatic clock gating is enabled or in the peripheral-specific RCGC registers when automatic clock gating is disabled. The system clock has the same source and frequency in sleep mode as it does during run mode.
The option to use the PLL VCO or an alternate oscillator source such as MOSC, PIOSC, Hibernation module RTC, or the LFIOSC is the same as described in Section 4.1.6.1. The RSCLKCFG register programming applies to sleep mode.
Additional sleep modes are available that lower the power consumption of the SRAM and flash memory. However, the lower power consumption modes have slower sleep and wake-up times.
NOTE
If the Cortex-M4F Debug Access Port (DAP) has been enabled, and the device wakes from a low-power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their run mode configuration. The DAP is usually enabled by software tools accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a WFI instruction. This stalls the execution of any code that accesses a peripheral register that might cause a fault. This loop can be removed for production software, because the DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (after a POR), the user can also reset the device. The DAP is not enabled unless it is enabled through the JTAG or SWD interface.