SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The SMBus interface is based on the I2C protocol; however, some differences exist between the two. These differences must be handled through software in order to make sure the SMBus protocol, including timing specifications, is met. Note that the SMBus 2.0 specification limits the maximum frequency of the interface to 100 KHz; as a result, I2C standard speed operation is used for SMBus.
The SMBus and I2C slave can extend the transaction if it is not ready by pulling the clock low. The SMbus specification allows the maximum time-out for such elongated transaction to be 25 to 35 ms. The I2C specification does not have this requirement. The I2C module supports a programmable count to support clock-low time-out for the master to error out and take action as required; this feature is explained in Section 19.3.1.6. Note that if transactions are extended, a time-out period should be programmed in the I2CMCLKOCNT register, and the CLKRIS bit in the I2CMRIS register should not be masked.
Unlike the I2C slave, the SMBus slave must respond with an ACK response to its address regardless of whether it is ready or not. As a result, the I2C slave sends an ACK response to its address and a NACK response on the data byte if it is not ready. The ARBLST bit in the I2CMCS register is set if there were any issues with the transfer. In addition, the slave can send a NACK at any time to force the master to stop sending additional bytes.
The I2C interface supports µDMA for efficient data handling. The µDMA operation needs FIFOs to be enabled for appropriate transfer type to perform I2C master for burst transfers and all types of slave transfers. The I2C interface is supported by two channels: one for Rx (I2C-to-Memory) and one for Tx (Memory-to-I2C) transfers. SeeSection 19.3.5 for more information.