SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
QSSI Clock Prescale (SSICPSR), offset 0x010
The SSICPSR register specifies the division factor which is used to derive the SSInClk from the system clock. The clock is further divided by a value from 1 to 256, which is 1 + SCR. SCR is programmed in the SSICR0 register. The frequency of the SSInClk is defined by:
SSInClk = SysClk / (CPSDVSR * (1 + SCR))
The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero.
SSICPSR is shown in Figure 23-14 and described in Table 23-10.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPSDVSR | ||||||||||||||||||||||||||||||
R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||