| 31-12 |
RESERVED |
R |
0x0 |
|
| 11 |
EOM |
R/W |
0x0 |
Stop Frame (End of Message). This bit is applicable when MODE is set to Advanced, Bi- or Quad- SSI. This bit is inserted into bit 12 of the TXFIFO data entry by the QSSI module.
0x0 = No change is transmission status.
0x1 = End of message (Stop Frame).
|
| 10 |
FSSHLDFRM |
R/W |
0x0 |
FSS Hold Frame
0x0 = Pulse SSInFss at every byte (the DSS bit in the SSICR0 register must be set to 0x7 (data size 8 bits) in this configuration)
0x1 = Hold SSInFss for the whole frame
|
| 9 |
HSCLKEN |
R/W |
0x0 |
High Speed Clock Enable. High speed clock enable is available only when operating as a master. For proper functionality of high speed mode, the HSCLKEN bit in the SSICR1 register should be set before any SSI data transfer or after applying a reset to the QSSI module. In addition, the SSE bit must be set to 0x1 before the HSCLKEN bit is set.
0x0 = Use Input Clock
0x1 = Use High Speed Clock
|
| 8 |
DIR |
R/W |
0x0 |
QSSI Direction of Operation
0x0 = TX (Transmit Mode) write direction
0x1 = RX (Receive Mode) read direction
|
| 7-6 |
MODE |
R/W |
0x0 |
QSSI Mode
0x0 = Legacy SSI mode
0x1 = Bi-SSI mode
0x2 = Quad-SSI Mode
0x3 = Advanced SSI Mode with 8-bit packet size
|
| 5-3 |
RESERVED |
R |
0x0 |
|
| 2 |
MS |
R/W |
0x0 |
QSSI Master/Slave Select. This bit selects Master or Slave mode and can be modified only when the QSSI is disabled ( SSE =0).
0x0 = The QSSI is configured as a master.
0x1 = The QSSI is configured as a slave.
|
| 1 |
SSE |
R/W |
0x0 |
QSSI Synchronous Serial Port Enable
0x0 = QSSI operation is disabled.
0x1 = QSSI operation is enabled.The HSCLKEN bit in the SSICR1 register should be set only after applying reset to the QSSI module and enabling the QSSI by setting the SSE bit, and before any SSI data transfer. All other bits in the SSICR1 register and all bits in SSICR0 register can only be programmed when the SSE is clear.
|
| 0 |
LBM |
R/W |
0x0 |
QSSI Loopback Mode
0x0 = Normal serial port operation enabled.
0x1 = Output of the transmit serial shift register is connected internally to the input of the receive serial shift register.
|