SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
QSSI Data (SSIDR), offset 0x008
The SSIDR register is 16-bits wide. When the SSIDR register is read, the entry in the receive FIFO that is pointed to by the current FIFO read pointer is accessed. When a data value is removed by the QSSI receive logic from the incoming data frame, it is placed into the entry in the receive FIFO pointed to by the current FIFO write pointer.
When the SSIDR register is written to, the entry in the transmit FIFO that is pointed to by the write pointer is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. Each data value is loaded into the transmit serial shifter, then serially shifted out onto the SSInDAT0/SSInTX pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.
SSIDR is shown in Figure 23-12 and described in Table 23-8.
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| RESERVED | DATA | ||||||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||