23.5.9 SSIICR Register (Offset = 0x20) [reset = 0x0]
QSSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
SSIICR is shown in Figure 23-18 and described in Table 23-14.
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Figure 23-18 SSIICR Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
EOTIC |
DMATXIC |
DMARXIC |
RESERVED |
RTIC |
RORIC |
| R-0x0 |
W1C-0x0 |
W1C-0x0 |
W1C-0x0 |
R-0x0 |
W1C-0x0 |
W1C-0x0 |
|
Table 23-14 SSIICR Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-7 |
RESERVED |
R |
0x0 |
|
| 6 |
EOTIC |
W1C |
0x0 |
End of Transmit Interrupt Clear. Writing a 1 to this bit clears the EOTRIS bit in the SSIRIS register and the EOTMIS bit in the SSIMIS register.
|
| 5 |
DMATXIC |
W1C |
0x0 |
QSSI Transmit DMA Interrupt Clear. Writing a 1 to this bit clears the DMATXRIS bit in the SSIRIS register and the DMATXMIS bit in the SSIMIS register.
|
| 4 |
DMARXIC |
W1C |
0x0 |
QSSI Receive DMA Interrupt Clear. Writing a 1 to this bit clears the DMARXRIS bit in the SSIRIS register and the DMARXMIS bit in the SSIMIS register.
|
| 3-2 |
RESERVED |
R |
0x0 |
|
| 1 |
RTIC |
W1C |
0x0 |
QSSI Receive Time-Out Interrupt Clear. Writing a 1 to this bit clears the RTRIS bit in the SSIRIS register and the RTMIS bit in the SSIMIS register.
|
| 0 |
RORIC |
W1C |
0x0 |
QSSI Receive Overrun Interrupt Clear. Writing a 1 to this bit clears the RORRIS bit in the SSIRIS register and the RORMIS bit in the SSIMIS register.
|