23.5.6 SSIIM Register (Offset = 0x14) [reset = 0x0]
QSSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared on reset.
On a read, this register gives the current value of the mask on the corresponding interrupt. Setting a bit clears the mask, enabling the interrupt to be sent to the interrupt controller. Clearing a bit sets the corresponding mask, preventing the interrupt from being signaled to the controller.
SSIIM is shown in Figure 23-15 and described in Table 23-11.
Return to Summary Table.
Figure 23-15 SSIIM Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
EOTIM |
DMATXIM |
DMARXIM |
TXIM |
RXIM |
RTIM |
RORIM |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 23-11 SSIIM Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-7 |
RESERVED |
R |
0x0 |
|
| 6 |
EOTIM |
R/W |
0x0 |
End of Transmit Interrupt Mask
0x0 = The end of transmit interrupt is masked.
0x1 = The end of transmit interrupt is not masked.
|
| 5 |
DMATXIM |
R/W |
0x0 |
QSSI Transmit DMA Interrupt Mask
0x0 = The transmit DMA interrupt is masked.
0x1 = The transmit DMA interrupt is not masked.
|
| 4 |
DMARXIM |
R/W |
0x0 |
QSSI Receive DMA Interrupt Mask
0x0 = The receive DMA interrupt is masked.
0x1 = The receive DMA interrupt is not masked.
|
| 3 |
TXIM |
R/W |
0x0 |
QSSI Transmit FIFO Interrupt Mask
0x0 = The transmit FIFO interrupt is masked.
0x1 = The transmit FIFO interrupt is not masked.
|
| 2 |
RXIM |
R/W |
0x0 |
QSSI Receive FIFO Interrupt Mask
0x0 = The receive FIFO interrupt is masked.
0x1 = The receive FIFO interrupt is not masked.
|
| 1 |
RTIM |
R/W |
0x0 |
QSSI Receive Time-Out Interrupt Mask
0x0 = The receive FIFO time-out interrupt is masked.
0x1 = The receive FIFO time-out interrupt is not masked.
|
| 0 |
RORIM |
R/W |
0x0 |
QSSI Receive Overrun Interrupt Mask
0x0 = The receive FIFO overrun interrupt is masked.
0x1 = The receive FIFO overrun interrupt is not masked.
|