SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
For enhanced modes of operation, the SSInFss signal can be programmed to assert low at the start of each byte transfer for one clock or the entire frame. This is configured by programming the FSSHLDFRM bit in the SSICR1 register. The EOM bit is also provided to signify end of frame transmission. This bit is embedded in the TXFIFO entry for use at the interface to deassert SSInFss at the appropriate time. The FSSHLDFRM bit can also be used when operating in 8-bit legacy SSI mode.
The functionality of the FSSHLDFRM bit for both legacy SSI mode and the enhanced modes are as follows:
| Mode | FSSHLDFRM | Description |
|---|---|---|
| Legacy mode | 0 |
For Freescale format, with SPH = 0, the SSInFss signal is deasserted (high) between continuous transfers. For SPH = 1, the SSInFss signal is asserted (low) between continuous transfers. For TI format, the SSInFss signal is deasserted (high) after every data transfer. |
| 1 | Not a valid combination as the SSInFSS signal is forced low even after transmission is completed and requires the FSSHLDFRM bit to be cleared to release the SSInFSS signal. | |
| Advanced, bi-, and quad-SSI mode | 0 | SSInFss is asserted low after every byte of data |
| 1 | New data written to the TX FIFO notifies SSInFss to assert low until the EOM bit is set with the last transfer, only after which the SSInFSS is asserted high. |