23.5.7 SSIRIS Register (Offset = 0x18) [reset = 0x8]
QSSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSIRIS is shown in Figure 23-16 and described in Table 23-12.
Return to Summary Table.
Figure 23-16 SSIRIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
EOTRIS |
DMATXRIS |
DMARXRIS |
TXRIS |
RXRIS |
RTRIS |
RORRIS |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x1 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 23-12 SSIRIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-7 |
RESERVED |
R |
0x0 |
|
| 6 |
EOTRIS |
R |
0x0 |
End of Transmit Raw Interrupt Status. This bit is cleared when a 1 is written to the EOTIC bit in the SSI Interrupt Clear (SSIICR) register.
0x0 = No interrupt.
0x1 = The transmit FIFO is empty, and the last bit has been transmitted out of the serializer.
|
| 5 |
DMATXRIS |
R |
0x0 |
QSSI Transmit DMA Raw Interrupt Status. This bit is cleared when a 1 is written to the DMATXIC bit in the SSI Interrupt Clear (SSIICR) register.
0x0 = No interrupt.
0x1 = The transmit DMA has completed.
|
| 4 |
DMARXRIS |
R |
0x0 |
QSSI Receive DMA Raw Interrupt Status. This bit is cleared when a 1 is written to the DMARXIC bit in the SSI Interrupt Clear (SSIICR) register.
0x0 = No interrupt.
0x1 = The receive DMA has completed.
|
| 3 |
TXRIS |
R |
0x1 |
QSSI Transmit FIFO Raw Interrupt Status. This bit is cleared when the transmit FIFO is more than half full.
0x0 = No interrupt.
0x1 = T he transmit FIFO is half empty or less.
|
| 2 |
RXRIS |
R |
0x0 |
QSSI Receive FIFO Raw Interrupt Status. This bit is cleared when the receive FIFO is less than half full.
0x0 = No interrupt.
0x1 = The receive FIFO is half full or more.
|
| 1 |
RTRIS |
R |
0x0 |
QSSI Receive Time-Out Raw Interrupt Status. This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt Clear (SSIICR) register.
0x0 = No interrupt.
0x1 = The receive time-out has occurred.
|
| 0 |
RORRIS |
R |
0x0 |
QSSI Receive Overrun Raw Interrupt Status. This bit is cleared when a 1 is written to the RORIC bit in the SSI Interrupt Clear (SSIICR) register.
0x0 = No interrupt.
0x1 = The receive FIFO has overflowed
|