25.1.5.1.1 Starting a New Hash

To start a new hash, follow these steps:

1. Set the ALGO bitfield in the SHA_MODE register, at offset 0x044, to 0x1, 0x2, or 0x3 to select SHA-1, SHA-224, or SHA-256, respectively.
2. Set the ALGO_CONSTANT bit in the SHA_MODE register to 1 to initialize all SHA Inner and Outer Digest n registers from SHA_ODIGEST_A and SHA_IDIGEST_A to SHA_ODIGEST_H and SHA_IDIGEST_H with their default values specified by the algorithm, and set the SHA_DIGESTCOUNT register to 0.
3. Set the CLOSE_HASH bit of the SHA Mode (SHA_MODE) register to let the SHA engine do the padding. If the Hash is computed in one shot, the length of the message can be any value up to 128 MB. To process an intermediate Hash digest, the CLOSE_HASH bit is set to 0, in which case the packets hashed must be 64 bytes; the last packet must be hashed with the CLOSE_HASH bit set to 1.
4. Specify the LENGTH field in the SHA Length (SHA_LENGTH) register of the hash data to process in bytes.

After the configuration is complete, the INPUT_READY status bit equals 1 in the SHA Interrupt Status (SHA_IRQSTATUS) register (regardless of whether or not the M_INPUT_READY bit in the SHA_IRQENABLE register is set). When this bit is set, it indicates the SHA engine can receive the data to process. Data must be written to the 16 × 32-bit SHA_DATA_n_IN registers that provide storage for one 64-byte block of data. Unless the CLOSE_HASH bit is set, all of the SHA_DATA_n_IN input buffers must be filled. Data can be written by single write accesses to the 16 registers from a processor or by a DMA transfer.

For µDMA transfers, the DMA_EN bit must be set in the SHA_SYSCONFIG register and the appropriate mask bits must be set in the SHA_DMAIM register before starting the new hash. Note that if the µDMA is used for transfers, the SHA_IRQENABLE register should be clear so all interrupts are generated through the µDMA interrupt registers.

The µDMA must be configured to transfer 16 data words of 32 bits each time it is triggered by a µDMA request from the SHA/MD5 Module. The 16 data words written are sent to the 16 SHA_DATA_n_IN registers.

The module detects that a 64-byte block is available, and then moves the data to a working register space for processing and asserts the INPUT_READY bit in the SHA_IRQSTATUS register to 1. If the DMA_EN bit in the SHA_SYSCONFIG register has been set to 1, a new µDMA request triggers a new block transfer; otherwise, the processor polls the INPUT_READY bit and writes the 16 data words of 32 bits when it equals 1.

This operation is repeated until the length of the message to hash is reached. The OUPUT_READY bit in the SHA_IRQSTATUS register then indicates that the hash operation is complete. If the IT_EN bit in the SHA_SYSCONFIG register is set, an interrupt (active low) is also generated to indicate the hash completion.

The processor can then read the eight digest registers A through H that contain the hash and/or HMAC result. If the hash is an intermediate result of a larger hash, the digest count register must also be read and saved.