5.2.4 SYSEXCIC Register (Offset = 0xC) [reset = 0x0]
System Exception Interrupt Clear (SYSEXCIC)
The SYSEXCIC register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
SYSEXCIC is shown in Figure 5-4 and described in Table 5-6.
Return to Summary Table.
Figure 5-4 SYSEXCIC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| W1C-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| W1C-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| W1C-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
FPIXCIC |
FPOFCIC |
FPUFCIC |
FPIOCIC |
FPDZCIC |
FPIDCIC |
| W1C-0x0 |
W1C-0x0 |
W1C-0x0 |
W1C-0x0 |
W1C-0x0 |
W1C-0x0 |
W1C-0x0 |
|
Table 5-6 SYSEXCIC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-6 |
RESERVED |
W1C |
0x0 |
|
| 5 |
FPIXCIC |
W1C |
0x0 |
Floating-Point Inexact Exception Interrupt Clear
Writing 1 to this bit clears the FPIXCRIS bit in the SYSEXCRIS register and the FPIXCMIS bit in the SYSEXCMIS register.
|
| 4 |
FPOFCIC |
W1C |
0x0 |
Floating-Point Overflow Exception Interrupt Clear
Writing 1 to this bit clears the FPOFCRIS bit in the SYSEXCRIS register and the FPOFCMIS bit in the SYSEXCMIS register.
|
| 3 |
FPUFCIC |
W1C |
0x0 |
Floating-Point Underflow Exception Interrupt Clear
Writing 1 to this bit clears the FPUFCRIS bit in the SYSEXCRIS register and the FPUFCMIS bit in the SYSEXCMIS register.
|
| 2 |
FPIOCIC |
W1C |
0x0 |
Floating-Point Invalid Operation Interrupt Clear
Writing 1 to this bit clears the FPIOCRIS bit in the SYSEXCRIS register and the FPIOCMIS bit in the SYSEXCMIS register.
|
| 1 |
FPDZCIC |
W1C |
0x0 |
Floating-Point Divide By 0 Exception Interrupt Clear
Writing 1 to this bit clears the FPDZCRIS bit in the SYSEXCRIS register and the FPDZCMIS bit in the SYSEXCMIS register.
|
| 0 |
FPIDCIC |
W1C |
0x0 |
Floating-Point Input Denormal Exception Interrupt Clear
Writing 1 to this bit clears the FPIDCRIS bit in the SYSEXCRIS register and the FPIDCMIS bit in the SYSEXCMIS register.
|