SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
System Exception Interrupt Mask (SYSEXCIM)
The SYSEXCIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit prevents the raw interrupt signal from being sent to the interrupt controller.
SYSEXCIM is shown in Figure 5-2 and described in Table 5-4.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FPIXCIM | FPOFCIM | FPUFCIM | FPIOCIM | FPDZCIM | FPIDCIM | |
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |