5.2.3 SYSEXCMIS Register (Offset = 0x8) [reset = 0x0]
System Exception Masked Interrupt Status (SYSEXCMIS)
The SYSEXCMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect.
SYSEXCMIS is shown in Figure 5-3 and described in Table 5-5.
Return to Summary Table.
Figure 5-3 SYSEXCMIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
FPIXCMIS |
FPOFCMIS |
FPUFCMIS |
FPIOCMIS |
FPDZCMIS |
FPIDCMIS |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 5-5 SYSEXCMIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-6 |
RESERVED |
R |
0x0 |
|
| 5 |
FPIXCMIS |
R |
0x0 |
Floating-Point Inexact Exception Masked Interrupt Status
This bit is cleared by writing 1 to the FPIXCIC bit in the SYSEXCIC register.
|
| 4 |
FPOFCMIS |
R |
0x0 |
Floating-Point Overflow Exception Masked Interrupt Status
This bit is cleared by writing 1 to the FPOFCIC bit in the SYSEXCIC register.
|
| 3 |
FPUFCMIS |
R |
0x0 |
Floating-Point Underflow Exception Masked Interrupt Status
This bit is cleared by writing 1 to the FPUFCIC bit in the SYSEXCIC register.
|
| 2 |
FPIOCMIS |
R |
0x0 |
Floating-Point Invalid Operation Masked Interrupt Status
This bit is cleared by writing 1 to the FPIOCIC bit in the SYSEXCIC register.
|
| 1 |
FPDZCMIS |
R |
0x0 |
Floating-Point Divide By 0 Exception Masked Interrupt Status
This bit is cleared by writing 1 to the FPDZCIC bit in the SYSEXCIC register.
|
| 0 |
FPIDCMIS |
R |
0x0 |
Floating-Point Input Denormal Exception Masked Interrupt Status
This bit is cleared by writing 1 to the FPIDCIC bit in the SYSEXCIC register.
|